For decades, the semiconductor industry has relied on a single, reliable trick: make transistors smaller.
Shrink the geometry, and chips get faster and more efficient at the same time.
This approach, known as geometric scaling, has been slowing down across the industry for years.
For Huawei, it stopped being an option altogether.
Manufacturing chips below the seven nanometre node requires extreme ultraviolet lithography machines, tools the company has been cut off from acquiring under US and allied export restrictions.
Rather than compete on a manufacturing process it cannot access, Huawei's engineers spent six years pursuing a different lever entirely.
Instead of shrinking the physical size of a transistor, they focused on shrinking the time it takes a signal to travel across a chip's most critical pathways, a value the company calls tau, written as the Greek letter τ.
Their flagship technique for compressing that delay is LogicFolding: taking circuitry that would normally sprawl flat across a single plane and folding it into vertically stacked tiers, bridged by extremely fine vertical connections.
In simpler terms, this is the difference between a traditional flat "circuit board" and what amounts to a "circuit cube," where circuitry is stacked upward rather than spread out.
Why stacking chips is supposed to cook them
The scepticism this technique invites is not unusual.
It reflects the industry's standard reaction to 3D chip stacking.
Stack active, switching transistors directly on top of other active, switching transistors, seal the whole assembly inside a smartphone, and conventional wisdom says the heat has nowhere to go.
Push temperatures past a certain threshold and a chip's clock speed throttles, its reliability degrades, and eventually it fails outright.
When Huawei first presented LogicFolding publicly, at a circuits and systems conference in May, the objection raised most forcefully in the room was precisely this one: heat, heat, and more heat.
Where the heat argument goes wrong
The rebuttal to that objection rests on a distinction that turns out to matter enormously.
That is the difference between the energy a chip spends actually computing, and the energy it spends simply moving data from one part of itself to another.
In a modern chip, it is the latter that dominates.
Charging and discharging the long metal wires that carry a signal across a chip consumes more energy than flipping the transistor gates that do the actual thinking.
An everyday comparison helps make the point.
For most office workers, the single largest chunk of a day's energy expenditure isn't the meetings or the spreadsheets, it's the commute.
A chip, according to Huawei's research, works the same way.
The gates do the thinking, and the wires do the commuting.
LogicFolding's entire purpose is to shorten that commute, by turning long horizontal wire runs into short vertical hops between stacked tiers.
Those hops are connected through a manufacturing process called hybrid bonding, which fuses two silicon wafers together at a near-atomic level.
What the measurements actually showed
Huawei's Kirin 2026 chip is the first commercial system-on-chip built using this technique, and is reportedly set to ship this month.
It packed 55% more transistors into the same area as its predecessor.
Given the conventional heat argument, power density should have climbed to match.
Instead, at matched performance, the chip's AI processing unit used 66% less power, its graphics unit used 58% less, and its main processor core used 41% less.
All of this happened while the chip ran measurably cooler than the flat, unstacked chip it replaced.
The explanation offered is that shortening the internal wiring let engineers cut clock speeds and reduce operating voltage substantially.
Because power consumption scales with the square of voltage, even modest voltage reductions produce outsized energy savings.
This was not a universal, effortless win across every part of the chip.
Its digital signal processor, which handles less parallel workloads, actually saw its power density rise in this first generation.
Huawei describes that result as a lesson that shrinking a chip's footprint and shrinking its energy use are not automatically the same thing.
The company says it has already corrected that specific problem in the following chip generation.
What this means going forward
The finding challenges a long-standing industry assumption about where chip heat actually comes from.
Correcting that assumption has opened up design headroom Huawei badly needed, given the manufacturing tools it cannot use.
Even so, this appears to be an early step rather than a final one.
Huawei describes its current approach as deliberately conservative, applying folding selectively rather than throughout the entire chip.
The company says unlocking the technique's full potential will take another three to five years of continued development across the wider industry.